The present invention relates to bipolar transistors, and more particularly to an epitaxial base bipolar transistor having a raised extrinsic base and methods of fabricating the same.
High-base resistance in bipolar transistors degrades both the minimum noise and power gain cutoff frequency. A key component of the aforesaid resistance is the extrinsic base resistance. In order to reduce the extrinsic base resistance, it is known to ion implant the base region adjacent to the emitter. Despite being capable of reducing the extrinsic base resistance, ion implantation of the base region causes transient enhanced diffusion of the implanted dopants which widens the intrinsic base, and diffuses the pedestal implant as well as the intrinsic base itself.
Additional diffusion width, which causes subsequent overlap of the implants, leads to high-capacitance devices. Moreover, this increased capacitance results in slower operating devices that have poor performance associated therewith.
FIGS. 1 and 2A are representative of prior art bipolar transistors in which the extrinsic base region is formed by ion implantation and activation annealing.
Specifically, FIG. 1 is a cross-sectional view through a prior art silicon germanium (SiGe) bipolar device 10 using implanted extrinsic base regions, while FIG. 2A is a top-down view of the raised portion of the device shown in FIG. 1.
Prior art bipolar device 10 of FIG. 1 comprises subcollector region (e.g., N+ doped) 14 formed in Si substrate 12 (e.g., N-type). The substrate also includes collector contact region 15 and isolation regions 16. A base region (e.g., P-type) 18 of silicon (mono-crystalline or epitaxial over the substrate, and polysilicon over the isolation regions) is located on top of the Si substrate. Base region 18 includes both intrinsic (P-doped) 18i and extrinsic (N-doped) 18e regions. The extrinsic base region surrounds the intrinsic region to a fixed depth below a Ge rich layer 20. In general, the polysilicon/epitaxial region, i.e., base region 18, is about 500-3000 xc3x85 thick. As stated above, within the base is a Ge rich layer of about 250-1500 xc3x85, located 50-500 xc3x85 from the top of the base.
On top of the base region is insulator 22 having an opening exposing the top of the base region. Overlapping this opening is polysilicon emitter (N+ doped) 24. Some of the doping from the emitter region is diffused into the base region. Surrounding the emitter region are dielectric spacers 26 and a cap layer which is formed on the emitter polysilicon.
Within the silicon substrate is a pedestal region 28 (N+ doped) extending from the subcollector into the base region, but not contacting the isolation regions. The highly doped extrinsic base region of the base extends laterally to contact the pedestal. As shown, prior art implantation and subsequent activation annealing causes overlap between the pedestal and base regions.
In FIG. 2A, the result of the extrinsic base region implant on resistance is shown. Note the effect of misalignment on the resistance between the emitter and the extrinsic base. This must be compared to the situation in FIG. 2B where no extrinsic base implant exists. The intrinsic portion of the base has a resistance of about 10,000 ohms/square while the extrinsic portion has a resistance of about 200 ohms/square. However, where the extrinsic base contacts or comes in proximity with the pedestal, a capacitance is associated with the PN junction. Equation (1) below shows the relationship between the important parameters:
fmaxxcex1ft/(RBCCB)xe2x80x83xe2x80x83(I)
where fmax is the maximum frequency at which there is still power gain, ft is the frequency at which the current gain goes to 1 (increases with higher pedestal doping), RB is the base resistance and is the sum of both intrinsic and extrinsic resistance, and CCB is the collector base capacitance (increases with higher pedestal doping).
In order to achieve higher performance and scale the device, the pedestal dose must be increased while keeping the extrinsic base resistance low. In current devices, this is a difficult problem as the ion dose increases.
In view of the above, there is thus a need to develop a new and improved method that is capable of forming a epitaxial base bipolar transistor in which both the base resistance and the device capacitance is decreased; The new method should avoid the use of ion implanting the base region since the same causes overlap of the diffused regions and increased device capacitance.
One object of the present invention is to provide an epitaxial base bipolar transistor having a low-base resistance in which the capacitance of the device is not increased.
A further object of the present invention is to provide an epitaxial base bipolar transistor having minimum noise and power gain cutoff frequency.
A still further object of the present invention is to provide an epitaxial base bipolar transistor having high-operating device performance and increased switching speeds as compared to prior art bipolar devices.
An even further object of the present invention is to provide an epitaxial base bipolar transistor wherein the emitter is self-aligned and centered to the base.
These and other objects and advantages are achieved in the present invention by utilizing a raised base structure and by providing a shallow extrinsic base profile utilizing a doped polysilicon layer as the diffusion source for the extrinsic base.
In accordance with one aspect of the present invention, methods of forming an epitaxial base bipolar transistor device having a raised extrinsic base are provided in which the base region is not doped by ion implantation.
In the first method of the present invention, the emitter region is formed prior to forming the base region. Specifically, the first method of the present invention comprises the steps of:
(a) growing at least an epitaxial single crystal layer on a single crystal semiconductor substrate;
(b) forming a raised emitter on a surface of said semiconductor substrate, said raised emitter including insulating material formed on at least sidewalls thereof;
(c) forming a raised extrinsic base on said surface of said semiconductor substrate, wherein the raised emitter and the raised extrinsic base are insulated by said insulating material; and
(d) diffusing dopant from the raised emitter and said raised extrinsic base so as to provide an emitter diffusion and an extrinsic diffusion in the single crystal semiconductor substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface.
In one preferred aspect of the present invention, the emitter to base surface height difference is less than 20% of the emitter junction depth.
The second method of the present invention forms the raised extrinsic base prior to formation of the emitter region. By forming the raised extrinsic base prior to emitter formation, the emitter will be self-aligned and centered to the base. Specifically, the second method of the present invention comprises the steps of:
(a) growing at least an epitaxial single crystal layer on a single crystal semiconductor substrate;
(b) forming a raised extrinsic base on said surface of said semiconductor substrate;
(c) forming a raised emitter on a surface of said semiconductor substrate, said raised emitter including insulating material formed on at least sidewalls thereof said insulating material electrically isolating said raised extrinsic base from said raised emitter; and
(d) diffusing dopant from the raised emitter and said raised extrinsic base so as to provide an emitter diffusion and an extrinsic diffusion in the single crystal semiconductor substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface.
In one preferred aspect of the second method of the present invention, the emitter to base surface height difference is less than 20% of the emitter junction depth.
In accordance with another aspect of the present invention, an intrinsic base bipolar transistor having a raised extrinsic base is provided. The inventive bipolar transistor comprises:
an epitaxial single crystal layer on a single crystal single substrate;
a raised emitter on the semiconductor surface;
a raised extrinsic base on the surface of the semiconductor substrate;
an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and
a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, said emitter extends to said substrate surface and said base extends to said substrate surface, and said emitter to base surface height difference is less than 20% of said emitter junction depth.
In one embodiment of the present invention, the emitter is self-aligned and centered to the base region.
A further aspect of the present invention is to provide a bipolar junction transistor in which the structure has resistance/capacitance control built therein. Specifically, the inventive bipolar junction transistor comprises:
a self-aligned base/emitter structure wherein a base-resistance is independently controlled by a diffusion source of variable thickness, and wherein the base-capacitance is independently variable clue to the combination of the thickness of the diffusion source and a thickness of an intrinsic-base epitaxial layer.